In the field of wireless communications such as television broadcasting and mobile phone communication, development of circuit technology using CMOS (Complementary Metal Oxide Semiconductor) devices are actively pursued. Also, synthesizer circuits are widely used in the field of wireless communications and are being designed on the level of CMOS process to develop synthesizer circuits with necessary characteristics, such as low noise, wide band, and low power consumption.
The synthesizer circuit is used to generate a local clock signal necessary for transmitting/receiving signals and includes a variable frequency divider therein. FIG. 23 illustrates the configuration of a conventional variable frequency divider. The variable frequency divider 100 comprises a clock source 101, a pre-divider 102, a phase shifter 103, and a divided clock signal generator 104.
The clock source 101 generates an input clock signal ck, and the pre-divider 102 divides the frequency of the input clock signal ck. The phase shifter 103 shifts the phase of the frequency divided clock signal to 0°, 90°, 180° and 270° to generate clock signals d1 to d4 with the respective phases, and outputs the generated clock signals from four ports, respectively.
On receiving a division ratio set signal indicative of an instructed division ratio to be set, the divided clock signal generator 104 generates a signal with the instructed division ratio from the clock signals d1 to d4, and outputs the generated signal as a frequency divided clock signal dout.
The variable frequency divider 100 performs the frequency division basically as follows: The frequency of the input clock signal ck is divided in a preset division ratio, then the phase of the thus-obtained clock signal is shifted to generate the four clock signals d1 to d4 with respective different phases, and logical operation is performed on predetermined ones of the clock signals to generate the frequency divided clock signal dout.
Generation of fifth (⅕) and third (⅓) frequency clock signals will be explained below as examples of the conventional frequency division. In the following, the operation of dividing the frequency of the input clock signal to generate a signal with a period (one clock period) corresponding to N clock periods of the input clock signal is referred to as 1/N frequency division (or Nth frequency division), and the clock signal obtained by subjecting the input clock signal to 1/N frequency division is referred to as Nth frequency clock signal. For example, the operation of dividing the frequency of the input clock signal to generate a signal with a period corresponding to two clock periods of the input clock signal is expressed as follows: The input clock signal is subjected to ½ frequency division to generate a second frequency clock signal.
FIG. 24 illustrates the manner of deriving a fifth frequency clock signal with fifth frequency division set by the division ratio set signal. The pre-divider 102 subjects the input clock signal ck to ¼ frequency division to generate a fourth frequency clock signal. The phase shifter 103 shifts the phase of the received fourth frequency clock signal every 90° and outputs clock signals d1 to d4 with phases 0°, 90°, 180° and 270°, respectively.
It is assumed that when the logical level of the clock signal da (a=1 to 4) and the logical level of the clock signal db (b=a+1 (when a=1, 2 or 3), b=1 (when a=4)) are both High, phase switching timing is generated, so that the divided clock signal generator 104 switches the phase by 90° (if the switching direction is positive, 0°→90°→180°→270°→0°→ . . . ).
t1: “t1” is a phase switching time interval over which the clock signals d1 (0) and d2 (90) both remain at the High level and during which switchover from the clock signal d1 (0) to the clock signal d2 (90) is performed.
Thus, before the phase switching time interval t1, the clock signal d1 (0) is output from the divided clock signal generator 104, and during the phase switching time interval t1, the High level is output from the divided clock signal generator 104. From the phase switching time interval t1 through to the next phase switching time interval t2, the switched clock signal d2 (90) is output from the divided clock signal generator 104.
t2: “t2” is a phase switching time interval over which the clock signals d2 (90) and d3 (180) both remain at the High level and during which switchover from the clock signal d2 (90) to the clock signal d3 (180) is effected.
Accordingly, during the phase switching time interval t2, the High level is output from the divided clock signal generator 104, and from the phase switching time interval t2 through to the next phase switching time interval t3, the switched clock signal d3 (180) is output from the divided clock signal generator 104.
t3: “t3” is a phase switching time interval over which the clock signals d3 (180) and d4 (270) both remain at the High level and during which switchover from the clock signal d3 (180) to the clock signal d4 (270) is carried out.
Thus, during the phase switching time interval t3, the High level is output from the divided clock signal generator 104, and from the phase switching time interval t3 through to the next phase switching time interval t4, the switched clock signal d4 (270) is output from the divided clock signal generator 104.
t4: “t4” is a phase switching time interval over which the clock signals d4 (270) and d1 (0) both remain at the High level and during which switchover from the clock signal d4 (270) to the clock signal d1 (0) is performed.
Accordingly, during the phase switching time interval t4, the High level is output from the divided clock signal generator 104, and from the phase switching time interval t4 through to the next phase switching time interval t1, the switched clock signal d1 (0) is output from the divided clock signal generator 104. The same operation as described above is repeated thereafter.
The frequency divided clock signal dout output from the divided clock signal generator 104 contains five input clock pulses ck in one period thereof, revealing that a fifth frequency clock signal is generated. The phase 90° of each fourth frequency clock signal corresponds to one period of the input clock signal ck, and thus one period of the fourth frequency clock signal contains four periods of the input clock signal ck.
Thus, by causing the divided clock signal generator 104 to perform a phase shift of +90° with respect to the fourth frequency clock signals, it is possible to obtain a frequency divided clock signal dout of which one period contains five (=4+1) periods of the input clock signal ck.
FIG. 25 illustrates the manner of obtaining a third frequency clock signal with third frequency division set by the division ratio set signal. It is assumed that when the logical levels of the two clock signals da and db are both High, the phase switching timing is generated, so that the divided clock signal generator 104 switches the phase by 90° in the negative direction (0°→270°→180°→90°→0°→ . . . ).
t11: “t11” is a phase switching time interval over which the clock signals d1 (0) and d4 (270) both remain at the High level and during which switchover from the clock signal d1 (0) to the clock signal d4 (270) is performed.
Thus, during the phase switching time interval t11, the High level is output from the divided clock signal generator 104, and from the phase switching time interval t11 through to the next phase switching time interval t12, the switched clock signal d4 (270) is output from the divided clock signal generator 104.
t12: “t12” is a phase switching time interval over which the clock signals d4 (270) and d3 (180) both remain at the High level and during which switchover from the clock signal d4 (270) to the clock signal d3 (180) is effected.
Accordingly, during the phase switching time interval t12, the High level is output from the divided clock signal generator 104, and from the phase switching time interval t12 through to the next phase switching time interval t13, the switched clock signal d3 (180) is output from the divided clock signal generator 104.
t13: “t13” is a phase switching time interval over which the clock signals d3 (180) and d2 (90) both remain at the High level and during which switchover from the clock signal d3 (180) to the clock signal d2 (90) is carried out.
Thus, during the phase switching time interval t13, the High level is output from the divided clock signal generator 104, and from the phase switching time interval t13 through to the next phase switching time interval t14, the switched clock signal d2 (90) is output from the divided clock signal generator 104.
t14: “t14” is a phase switching time interval over which the clock signals d2 (90) and d1 (0) both remain at the High level and during which switchover from the clock signal d2 (90) to the clock signal d1 (0) is performed.
Accordingly, during the phase switching time interval t14, the High level is output from the divided clock signal generator 104, and from the phase switching time interval t14 through to the next phase switching time interval t11, the switched clock signal d1 (0) is output from the divided clock signal generator 104. The same operation as described above is repeated thereafter.
The frequency divided clock signal dout output from the divided clock signal generator 104 contains three input clock pulses ck in one period thereof, indicating that a third frequency clock signal is generated. The phase 90° of each fourth frequency clock signal corresponds to one period of the input clock signal ck, and one period of the fourth frequency clock signal contains four periods of the input clock signal ck. Thus, by causing the divided clock signal generator 104 to perform a phase shift of −90° with respect to the fourth frequency clock signals, it is possible to derive a frequency divided clock signal dout of which one period contains three (=4−1) periods of the input clock signal ck.
As a conventional technique, there has been proposed a frequency divider in which output patterns obtained by dividing the frequency of a reference clock signal in predetermined ratios are stored beforehand and, in accordance with the generation pattern of the input reference clock signal, a corresponding output pattern is read out to output a frequency divided signal (see, e.g., Japanese Laid-open Patent Publication No. 07-314248 (paragraph nos. [0035] to [0037], FIG. 1)).
As explained above, in the variable frequency divider 100, the divided clock signal generator 104 internally performs the phase switching to generate the frequency divided clock signal dout. In order to variably set the division ratio as desired, however, complicated timing control is needed for the phase switching, and it has been difficult to carry out variable frequency division in a desired division ratio by using only a digital circuit with simple configuration.
In most of conventional variable frequency dividers, necessary frequency division patterns are prepared beforehand as embedded software, for example, to implement variable frequency division, as in the above conventional technique (Japanese Laid-open Patent Publication No. 07-314248). Accordingly, there has been a demand for variable frequency dividers constituted by a small number of circuit elements and capable of performing predetermined frequency division operations.
Meanwhile, in the variable frequency divider 100, where the phase switching timing is generated when the clock signals da and db are both at the same logical level, as explained above with reference to FIGS. 22 and 23, a frequency divided clock signal dout free of waveform degradation is output (although in the above, High level is exemplified as the logical level, the frequency division is also normally performed in the case where the phase switching timing is generated when the two clock signals da and db are both at the Low level).
If the phase switching timing deviates, however, a problem arises in that the waveform of the frequency divided clock signal dout degrades. Referring now to FIGS. 24 and 25, waveform degradation of the frequency divided clock signal dout attributable to deviation of the phase switching timing will be explained.
Let us consider the case where, with respect to the clock signals d1 to d4 output from the phase shifter 103, the divided clock signal generator 104 performs a phase shift of +90° from the currently output clock signal da (a=1 to 4) to the clock signal db (b=a+1 (when a=1, 2 or 3), b=1 (when a=4)) for the phase switching.
FIG. 26 illustrates phase switching accompanying pulse splitting, or more specifically, timing waveforms while a frequency divided clock signal dout1 with waveform degradation is output from the divided clock signal generator 104. In this example, the phase switching timing is generated when the logical levels of the clock signals da and db are High and Low, respectively.
Phase Switching At Timing t21: The divided clock signal generator 104 performs switchover from 0° to 90° while the clock signal d1 (0) is being output. Suppose that, in this case, phase switching timing t21 is generated when the logical levels of the clock signals d1 (0) and d2 (90) are High and Low, respectively, with the result that the clock signal is switched from the clock signal d1 (0) to the clock signal d2 (90).
From the timing t21 through to the next switching timing t22, the switched clock signal d2 (90) is output as the frequency divided clock signal dout1 (before the timing t21, the clock signal d1 (0) is output as the frequency divided clock signal dout1).
Phase Switching at Timing t22: The divided clock signal generator 104 performs switchover from 90° to 180° when the clock signal d2 (90) is being output. If, in this case, the phase switching timing t22 is generated when the clock signals d2 (90) and d3 (180) are High and Low, respectively, the clock signal is switched from the clock signal d2 (90) to the clock signal d3 (180). As a result, from the timing t22 through to the next switching timing t23, the switched clock signal d3 (180) is output as the frequency divided clock signal dout1.
Phase Switching at Timing t23: The divided clock signal generator 104 performs switchover from 180° to 270° while the clock signal d3 (180) is output. In this case, if the phase switching timing t23 is generated when the clock signals d3 (180) and d4 (270) are High and Low, respectively, the clock signal is switched from the clock signal d3 (180) to the clock signal d4 (270). Consequently, from the timing t23 through to the next switching timing, the switched clock signal d4 (270) is output as the frequency divided clock signal dout1.
If the phase switching timing is generated when the logical levels of the clock signals da and db are High and Low, respectively, pulse splitting occurs in the frequency divided clock signal dout1, as illustrated in FIG. 26, so that the frequency divided clock signal dout1 has a degraded waveform, compared with the frequency divided clock signal dout obtained while the frequency division is performed normally. Also, because of the waveform degradation, the frequency divided clock signal dout1 contains two pulses a0-1 and a0-2 per period a0 of the frequency divided clock signal dout, and thus the frequency division performed is not a desired one.
FIG. 27 illustrates phase switching accompanying pulse splitting, or more specifically, timing waveforms while a frequency divided clock signal dout2 with waveform degradation is output from the divided clock signal generator 104. In this example, the phase switching timing (t24 to t26) is generated when the logical levels of the clock signals da and db are Low and High, respectively (since the basic operation of the phase switching is identical with that explained above with reference to FIG. 26, description thereof is omitted).
If the phase switching timing is generated when the logical levels of the clock signals da and db are Low and High, respectively, as illustrated in FIG. 27, pulse splitting occurs in the frequency divided clock signal dout2, and therefore, the frequency divided clock signal dout2 has a degraded waveform, compared with the frequency divided clock signal dout obtained during the normal frequency division. Also, due to the waveform degradation, the frequency divided clock signal dout2 contains two pulses b0-1 and b0-2 per period b0 of the frequency divided clock signal dout, and thus the frequency division performed is not a desired one.
Thus, in the variable frequency divider, pulse splitting occurs in the frequency divided clock signal dout unless the phase switching is executed at proper timing. It is therefore necessary to perform phase shift control at such timing that the pulse splitting is avoided.
Further, since the variable frequency divider 100 is constituted by a digital circuit, there is another problem that glitch, which is commonly observed in digital circuits, may possibly be caused. Glitch denotes a transient noise pulse.
FIG. 28 illustrates an example of how glitch occurs. An AND gate is input with signals c1 and c2 and outputs a signal c3. At a change point of the input signals c1 and c2, the input signal c1 changes from Low to High while the input signal c2 changes from High to Low, for example, and because of a time difference between the input signals c1 and c2, an unwanted pulse (glitch) is output as the output signal c3. Glitch is a cause of malfunction, and therefore, the circuit needs to be designed so as to remove the cause of occurrence of glitch.